As a miniaturization technology of an integrated circuit progresses, the number of elements that can be implemented on one chip increases.
Previously, a circuit design using a synchronous method that distributes a synchronous signal called a clock throughout a chip and concurrently drives elements on the chip at clock edges was predominant.
However, as the number of the elements increases, a ratio of delay time of a signal that flows between the elements on the circuit (chip) to clock cycle time becomes greater. Therefore, it is difficult to cause the clock edges to arrive at all elements at the same time.
There is proposed a method that divides a system implemented on a chip into a plurality of functional blocks according to functions, and restricts an area where the clock edges are caused to arrive at the same time to the elements that are included in each functional block, thereby arbitrarily setting a timing at which the clock arrives at the elements between the functional blocks (in other words, an arrival timing of the clock edges is set as desired between different functional blocks and the clock edges are cause to arrive simultaneously at the elements that are included in the same functional block).
This is a circuit design method called Globally Asynchronous, Locally Synchronous (GALS) method.
Recently, the Globally Asynchronous, Locally Synchronous method mentioned above is becoming a main circuit design method.
When a circuit is designed using the GALS method, an asynchronous logic circuit is used as a circuit for data communication between functional blocks. The asynchronous logic circuit is a logic circuit that operates by making registers of a transfer source and a transfer destination to operate cooperatively between registers that perform data transfer using a handshake signal instead of using a clock.
A pair of a request signal and an acknowledgment signal is used as the handshake signal. A memory request signal of data is transferred from a transfer source register to a transfer destination register with data.
When no untransferred data remains in the transfer destination register upon receiving a data storage request, the transfer destination register stores the arrived data and transfers a storage completion acknowledgment indicating that the storage of the arrived data has been completed, to the transfer source register. On the other hand, when untransferred data remains in the transfer destination register, the transfer destination register waits without transferring the storage completion acknowledgment to the transfer source register until the transfer of the untransferred data is completed.
The transfer source register regards the stored data as having been transferred and prepares for a next data transfer upon receiving the storage completion acknowledgment from the transfer destination register.
Thus, it is possible for the asynchronous logic circuit to notify congestion on a data transfer route in the direction of the origin by using the handshake signal. Therefore, the functional blocks each of which is operated by the asynchronous clock can be made to operate cooperatively by receiving the congestion acknowledgment at the functional block that is the origin of the data transfer and suspending the transfer.
There are four-phase type and two-phase type handshake signal communication methods for an asynchronous logic circuit.
The four-phase type handshake signal communication is performed by sending the data memory request and the storage completion acknowledgment as voltage levels of a memory signal and an acknowledgment signal. When both the request signal and the acknowledgment signal between two registers that send and receive the data in the asynchronous logic circuit are in a low-voltage condition, the data memory request is sent when the request signal is brought into a high-voltage condition, and the storage completion acknowledgment is sent when the acknowledgment signal is brought into the high-voltage condition.
In the four-phase type handshake signal communication, both the request signal and the acknowledgment signal are restored to the low-voltage condition after the data transfer prior to the next data transfer.
The two-phase type handshake signal communication is performed by sending the data memory request and the storage completion acknowledgment as transitions of the memory signal and the acknowledgment signal. When both the request signal and the acknowledgment signal between two registers that send and receive the data in the asynchronous logic circuit are in the low-voltage condition, the data memory request at a first data communication is sent by a rising edge transition of the request signal, and the storage completion acknowledgment is sent by a rising edge transition of the acknowledgment signal.
As a result, the request signal and the acknowledgment signal are brought into the high-voltage condition by the first data communication. When a second data communication is performed from the condition, the data memory request is sent by a falling edge transition of the request signal, and the storage completion acknowledgment is sent by a falling edge transition of the acknowledgment signal.
Comparing the transfer speeds, the two-phase type has an advantage of higher speed over the four-phase type. This is because the four-phase type needs two reciprocating handshake signal communications to complete one data transfer, but the two-phase type needs only one reciprocating communication.
Therefore, the two-phase type can achieve the data transfer speed two times faster than that of the four-phase type in theory.
On the other hand, comparing the circuit configurations, the four-phase type has an advantage of a simpler configuration over the two-phase type. The four-phase type can use a level sensitive latch and a flip-flop that operates at one of a rising edge transition and a falling edge transition of a control signal, as a memory element used for a register. Therefore, the asynchronous logic circuit for the four-phase type handshake signal communication can be configured only by logic cells that have recently been widely used.
On the other hand, it is necessary for the asynchronous logic circuit for the two-phase type handshake signal communication to be configured with a flip-flop that operates in both directions of the control signal transitions as described in Non-Patent Document 1, or with an element that alternately changes two output signals according to the transitions in both directions of the control signal, as well as a level sensitive latch and a flip-flop that operates at one of the control signal transitions as described in Non-Patent Document 2.
However, most of the flip-flops that operate due to the both directions of the control signal transitions and the element that alternately changes two output signals according to the both directions of the control signal transitions are not prepared in a logic cell library. Therefore, it is practically almost impossible to design the asynchronous logic circuit that controls the two-phase type handshake signal communication.
Not only the register but also an asynchronous functional block that is necessary for the design of the asynchronous logic circuit that connects synchronous functional blocks in the circuit using the GALS method has a simply configuration in the four-phase type compared with the two-phase type.
As an example of the asynchronous functional block that is necessary for the design of the asynchronous logic circuit that connects the synchronous functional blocks, there is an arbitration circuit that arbitrates a plurality of input request signals and outputs one of the request signals.
FIG. 1 shows a configuration of a regulator circuit for the four-phase type handshake signal communication described in Non-Patent Document 3. Request signals Ri0, Ri1 and an acknowledgment signal Ao are supplied to an arbitration circuit 100. Acknowledgment signals Ai0, Ai1, a request signal Ro, and arbitration result signals Gr0, Gr1 are output from the arbitration circuit 100. The arbitration circuit 100 includes a mutual exclusion module 110, a preceding handshake completion module 120, an output request signal generation module 130, and an output acknowledgment signal generation module 140. The mutual exclusion module 110 includes a first-arrival signal selection module 111 and a wrong signal propagation prevention module 112.
Each module in the arbitration circuit 100 includes a typical combinational logic cell and a feedback loop.
A Muller's C element that configures the output acknowledgment signal generation module 140 is a state memory element that waits for two input signals. If conditions are satisfied, the element changes the output signal. If conditions are not satisfied, the element does not change but maintains the output signal.
A Muller's C element 200 shown in FIG. 2(a) has input terminals A, B and an output terminal Y.
The Muller's C element 200 operates so as to output Y=0 when the input signals are A=0 and B=0, and output Y=1 when the input signals are A=1 and B=1. Further, the Muller's C element 200 does not change but maintains the output signal when the input signals are A=0 and B=1 or A=1 and B=0.
For example, assume that the Muller's C element 200 is supplied with the input signals A=1 and B=1 and that the output signal is Y=1. Then, even though one of the input signals A and B changes and the input signals become A=0 and B=1 or A=1 and B=0, the output signal is maintained as Y=1. Further, also when the Muller's C element 200 is supplied with the input signals A=0 and B=0 and the output signal is Y=0, even though one of the input signals A and B changes and the input signals become A=1 and B=0 or A=0 and B=1, the output signal is maintained as Y=0.
Thus, the Muller's C element 200 outputs different values in accordance with a value obtained immediately before the combination of the signals supplied, even though the same combination of the input signals A=0 and B=1 is given.
Relations between the input signals and the output signals of the Muller's C element 200 are shown in FIG. 2(b). Here, Y (t−1) indicates a value of an output signal Y before one of the input signals A and B changes. If one of the input signals A and B changes from the state where the input signals are A=0 and B=0, Y (t−1) becomes “0”. If one of the input signals A and B changes from the state where the input signals are A=1 and B=1, Y (t−1) becomes “1”.
The Muller's C element 200 performs a crucial function in the asynchronous logic circuit by the waiting function and the state storage function.
For example, the output acknowledgment signal generation module 140 in the arbitration circuit 100 shown in FIG. 1 includes two Muller's C elements. The output acknowledgment signals Ai0 and Ai1 of the arbitration circuit 100 are generated as follows by the arbitration result signals Gr0 and Gr1 and the input acknowledgment signal Ao.
If Gr0=1 and Ao=1, then Ai0=1.
If Gr1=1 and Ao=1, then Ai1=1.
If Gr0=0 and Ao=0, then Ai0=0.
If Gr1=0 and Ao=0, then Ai1=0.
The restriction that the output acknowledgment signals Ai0 and Ai1 cannot be changed until the condition as well as the above conditions are satisfied is imposed, upon generating the output acknowledgment signals Ai0 and Ai1 of the arbitration circuit 100. The Muller's C elements are used in the output acknowledgment signal generation module 140 to achieve such an operation.
The reason why the arbitration circuit that performs the four-phase type handshake has the simple configuration as shown FIG. 1 is that there is no need for the four-phase arbitration circuit to be configured to store conditions of the handshake communication because the memory request and the completion acknowledgment are sent as the voltage levels.
For example, assume that the request signal Ri0 has arrived earlier than the other request signal Ri1. The request signals in the four-phase type are sent as signal levels Ri0=1 and Ri1=1, respectively. The four-phase arbitration circuit 110 can hold the signal level of the request signal Ri1=1 that has arrived later, and keep waiting for completion of the handshake by the other request signal Ri0=1. This is because it is possible to indicate that the processing corresponding to the request signal is not completed only by the signal level of Ri1=1.
On the other hand, in the two-phase type, the state of the handshake communication is unclear only by the voltage level because the storage request and the completion acknowledgment are sent as a signal transition of the handshake signal.
For example, assume that the request signal levels are changed from Ri0=Ri1=0 to Ri0=1, Ri1=1 in order. If the request at the rising edge of the request signal Ri0 that has arrived earlier is immediately started to be processed, Ri1 is maintained as Ri1=1 until the handshake signal communication at the rising edge of the signal Ri0 is completed.
However, in the two-phase type, it is impossible to indicate that the handshake communication at the rising edge of the request signal Ri1 is not started, because the handshake communication at the rising edge of the request signal Ri1 may have already been started only in the case where the signal state is Ri1=1.
Therefore, the two-phase type arbitration circuit has to store information indicating that the request at the rising edge of the request signal Ri1 that has arrived later is not processed.
The configuration of the two-phase type arbitration circuit becomes extremely complex because the storage of information indicating that the request by the signal transition of Ri1 is not processed must be caused not only by the signal transitions of both the rising edge and the falling edge of Ri1 but also by the signal transitions of both the rising edge and the falling edge of the input acknowledgment signal Ao. Therefore, the configuration of the two-phase type arbitration circuit is much larger than that of the four-phase arbitration circuit.
The technique that may achieve both the simplicity of the four-phase type circuit and the high-speed performance of the two-phase type is disclosed in Patent Document 1.
[Patent Document 1]
    Japanese Patent No. 3892323[Non-Patent Document 1]    S. Furber et al, “Four-phase Micro-pipeline Latch Control Circuits,” IEEE Transaction on VLSI Systems, Vol. 4, No. 2, pp. 247-253, June, 1996.[Non-Patent Document 2]    K. Y. Yun et al, “High-Performance Asynchronous Pipeline Circuits,” IEEE Int'l Symposium on Advanced Research on Asynchronous Circuits and Systems, pp. 17-28, March, 1996.[Non-Patent Document 3]    Jens Sparso and S. Furber, “Principles of Asynchronous Circuit Design: A Systems Perspective,” Kluwer Academic Publishers, pp. 57-80, December, 2001.